1. Field of the Invention
This invention relates generally to phase lock loops implemented in communication devices and systems. Specifically, this invention relates to a hybrid phase lock loop, which includes a digital component, an analog component and a loop monitor for switching between the digital control loop and the analog control loop.
2. Description of the Prior Art
The current state of modern communication systems describes various forms of phase lock loops (hereinafter "PLL") and voltage controlled oscillators (hereinafter "VCO") to synchronize transceivers with communication frequencies.
Referring to FIG. 1, one form of the genus of the PLL is the analog version, which is well known to those skilled in the art of telecommunications and is briefly described below. The analog PLL genus is characterized by a reference oscillator coupled to a harmonic frequency multiplier. The harmonic frequency multiplier, which produces a frequency comb that varies in amplitude over frequency, is coupled to a frequency/phase detector. The output of the frequency/phase detector is coupled to a loop filter, which typically is a low pass filter. The output of the loop filter is coupled to a VCO that produces a feedback signal to the frequency/phase detector. When the VCO output matches the reference oscillator in both frequency and phase, the two signals are essentially canceled by the frequency/phase detector which produces a null or zero output. A mismatch in frequency or phase will produce a signal that is sent to the VCO via the loop filter for synchronizing the PLL.
The advantage of the analog PLL genus is that there is relatively low phase noise produced by the electronic circuit. Low noise is desirable because it minimizes the opportunity for frequency or phase errors. Thus, once the analog PLL locks on to the incoming signal the possibility of the circuit losing the lock is relatively small.
A fundamental disadvantage of the analog PLL is a tendency to arbitrarily lock to any harmonic of the reference frequency that falls within the tuning range of the VCO. In order to force the analog PLL to reliably lock to a particular frequency in spite of the effects of the environment, manufacturing variations and component aging, it is necessary to reduce the tuning ranger of the VCO to cover only the single desired harmonic of the reference frequency. If it is desired that the analog PLL be capable of locking to one of several frequencies, it is necessary to have a separate VCO with a narrow tuning ranger for each frequency. Multiple VCOs will add to the complexity and cost of the design.
Referring to FIG. 2, a simple form of the digital PLL genus, which is also known to those skilled in the art, is illustrated. The digital PLL is characterized by a reference oscillator coupled to digital frequency divider. The output of the digital frequency divider is coupled to the frequency/phase detector. The frequency/phase detector is coupled to the low pass filter, whose output is coupled to the VCO. The VCO produces a feedback signal that is coupled to a second digital frequency divider which in turn is coupled to the frequency/phase detector.
The advantage of the digital PLL genus is that the two digital frequency dividers are programmable by an external source for high bandwidth and resolution. Thus, the digital implementation of the PLL provides for excellent control for steering or tuning the frequency synthesizer. Furthermore, the digital control capability affords multi-frequency tuning over a broad band.
A fundamental disadvantage of the digital PLL genus is that excessive noise is intrinsic to the digital nature of the design. Excessive noise results in the decreased performance of the phase lock loop.
The hybrid PLL incorporates features of both the analog and digital PLL. Rudimentary hybrids function by allowing the digital PLL with its superior tuning capability to initiate the frequency sweep and closing the digital loop. Once the digital loop is closed, the digital circuitry then switches control to the analog loop. The digital loop maintains its own phase lock even after switching control to the analog loop. Furthermore, the digital loop will monitor the frequency lock and will resume control and re-initiate the lock sequence if phase or frequency perturbations are sensed.
The detriments of these hybrid circuits are that phase perturbations which are endemic to the digital circuitry, but to which the analog circuitry are relatively immune, will trigger the digital circuitry to reinitiate the lock unnecessarily. These unnecessary and unwanted reinitializations result in catastrophic loss of telecommunications data.
Therefore, a need existed to provide a hybrid analog-digital PLL that is capable of multi-frequency synthesis that will address that problem of premature, unwanted control resumption of and reintialization by the digital PLL once the loop has been switched to the analog circuitry.